1. Field of the Invention
This invention relates to a semiconductor memory device, specifically to a semiconductor memory device that reads out data stored in a memory cell by comparing a data voltage corresponding to a cell current of the memory cell with a predetermined reference voltage.
2. Description of the Related Art
In recent years, electrically erasable and programmable nonvolatile memories or EEPROMs (Electrically Erasable Programmable Read Only Memories) are widely used in electronic equipment such as mobile phones and digital still cameras. The EEPROM is provided with a memory cell having a floating gate, a source and a drain. It stores binary data or more than two-level data according to whether electric charges are stored in the floating gate or not, and the stored data is read out by sensing a difference in a cell current flowing between the source and the drain, which varies depending on whether the electric charges are stored in the floating gate or not.
In this case, a read-out circuit provided in the EEPROM converts the cell current flowing through the memory cell into a data voltage, and judges the data (“0” or “1”) stored in the memory cell by comparing the data voltage with a predetermined reference voltage.
FIG. 9 is a circuit diagram of the read-out circuit in the EEPROM described above. The read-out circuit is composed of a current-voltage conversion circuit 1 (pre-sense amplifier) and a sense amplifier 2 (main sense amplifier). The current-voltage conversion circuit 1 is composed of a P channel type MOS transistor T6 having a source, to which a power supply voltage Vdd is applied, and a gate and a drain connected with each other (diode connection). A drain of a memory cell MC is connected to the drain of T6 through a bit line BL. A source of the memory cell MC is connected to a source line SL, while its gate is connected to a word line WL. A cell current Icell of the memory cell MC flows into the bit line BL, and is converted into a data voltage Vdata by the current-voltage conversion circuit 1.
The sense amplifier 2 is made of a common differential amplifier, and amplifies a difference between the data voltage Vdata and a reference voltage Vref. The sense amplifier 2 is composed of N channel type MOS transistors T1 and T2 that form a differential pair, P channel type MOS transistors T3 and T4 that form a current mirror, each of the MOS transistors T3 and T4 being connected with each of the MOS transistors T1 and T2 respectively, and an N channel type MOS transistor T5 that is connected with a common source of the MOS transistors T1 and T2.
The power supply voltage Vdd is applied to a common source of the MOS transistors T3 and T4. The data voltage Vdata from the current-voltage conversion circuit 1 is applied to a gate of the MOS transistor T1. The reference voltage Vref is applied to a gate of the MOS transistor T2. A sense enable signal SEN is applied to a gate of the MOS transistor T5.
Operations of the read-out circuit are hereafter described referring to FIG. 9 and FIG. 10. In this case, the source line SL is grounded, while a read-out voltage is applied to the bit line BL. When a voltage on the word line WL rises to an H level (Vdd, for example), there flows the cell current Icell that corresponds to the data stored in the memory cell MC. In general, a value of the cell current Icell is in the order of 0 to several tens of microamperes. When the data in the memory cell MC is “0” (programmed state), the value of the cell current Icell is a smaller value (close to a minimum value). When the data in the memory cell MC is “1” (erased state), the value of the cell current Icell is a larger value (close to a maximum value). The current-voltage conversion circuit 1 converts the cell current Icell into the data voltage Vdata.
After that, when the sense enable signal SEN rises to the H level (Vdd, for example), the MOS transistor T5 is turned on to activate the sense amplifier 2. With this, the sense amplifier 2 judges the data (“0” or “1”) stored in the memory cell MC by comparing the data voltage Vdata with the reference voltage Vref.
FIG. 10 shows correlations among the data voltage Vdata, the cell current Icell and the reference voltage Vref. The cell current Icell at an intersection of a Vdata-Icell curve and each of the reference voltages Vref1, Vref2 and Vref3 represents corresponding each of threshold cell currents Icell1, Icell2 and Icell3, respectively. That is, the data is judged to be “0” when the cell current Icell of the memory cell is smaller than a set threshold cell current, and the data is judged to be “1” when the cell current Icell is larger than the set threshold cell current.
An input operating voltage range (gate voltage range of the MOS transistors T1 and T2), in which the sense amplifier 2 operates normally, is from a lower limit voltage Vmin to an upper limit voltage Vmax.
In this case, Vmin and Vmax are represented by equations Vmin=Vt(T1)+Vds(T5), and Vmax=Vdd−Vds(T3)+Vt(T1), respectively. Vt(T1) denotes a threshold voltage of the MOS transistors T1 and T2, Vds(T5) denotes a voltage between a source and a drain of the MOS transistor T5, and Vds(T3) denotes a voltage between the source and a drain of the MOS transistor T3 (voltage drop across a diode).
Therefore, it is required that the reference voltage Vref is at least contained within the input operating voltage range. As shown in FIG. 10, the threshold cell current is set at Iref1 in the case of normal read-out, and the reference voltage Vref is accordingly set at Vref1 which is at the center of the input operating voltage range or in the vicinity thereof.
In general, the EEPROM has a function to judge the written-in data, which is referred to as verify. There are two kinds of verify that are erase verify and program verify. The erase verify judges whether the data in the memory cell MC is erased or not, in other words, whether the data stored in the memory cell MC is “1” or not. In this case, the threshold cell current is set to a condition that is severe with the data “1”, that is, the threshold cell current is set to Iref1 that is larger than Iref1. The reference voltage Vref is changed accordingly to Vref2 that is lower than Vref1. That is to compensate the operations of the EEPROM, considering variations and a change over time in the cell current Icell.
On the other hand, the program verify judges whether the data “0” is programmed to the memory cell MC correctly or not. In this case, the threshold cell current is set to a condition that is severe with the data “0”, that is, the threshold cell current is set to Iref3 that is smaller than Iref1. The reference voltage Vref is changed accordingly to Vref3 that is higher than Vref1.
Technologies mentioned above are disclosed in Japanese Patent Application Publication No. 2008-140431, for example.
As described above, the reference voltage Vref is changed in order to modify the threshold cell current at the time of verify in the conventional read-out circuit. As a result, the reference voltage Vref3 at the time of the program verify approaches the upper limit voltage Vmax of the input operating voltage range of the sense amplifier 2, while the reference voltage Vref2 at the time of the erase verify approaches the lower limit voltage Vmin of the input operating voltage range. Depending on the setting of the threshold cell current, it could happen that the reference voltage Vref2 or Vref3 at the time of verify is not contained within the input operating voltage range. Therefore, there is a possibility that a resolution to read-out the data would be reduced or a malfunction in reading out the data would occur.
Particularly when the power supply voltage Vdd is reduced to about 1.8 V, for example, it is increasingly difficult to contain the reference voltages Vref2 and Vref3 at the time of verify within the input operating voltage range because the input operating voltage range of the sense amplifier 2 becomes so narrow as about 0.8 V-1.6 V.